1. Technology Field
The present invention relates to a data reading method for a rewritable non-volatile memory module and particularly to a data reading method capable of effectively re-adjusting threshold voltages to correctly read data, and a memory controller and a memory storage apparatus using the method.
2. Description of Related Art
The growth of digital cameras, camera mobile phones, and MP3 players has been rapid in recent years. Consequently, demands of consumers for storage media of digital contents have increased drastically. Since flash memory has a characteristics of non-volatile data, energy saving, compact size, and without mechanical construction, the flash memory is suitable for users to carry on bodies as the storage media for transferring and exchanging the digital contents. Solid State Drive (SSD) is an example of utilizing the flash memory as the storage media, and has been widely applied in the computer host as a main hard disk.
A flash memory may be classified into a NOR flash memory or a NAND flash memory. Additionally, a NAND flash memory may be classified into a Multi Level Cell (MLC) NAND flash memory or a Single Level Cell (SLC) NAND flash memory according to the number of bits which each memory cell thereof is capable of storing. Each memory cell can store one bit of data in a SLC NAND flash memory, and each memory cell can store at least two bits of data in a MLC NAND flash memory. For example, taking a 4 level cell NAND flash memory as an example, each memory cell may store 2 bits of data (i.e., “11”, “10”, “00” or “01”).
In a flash memory, memory cells are linked through bit lines and word lines to form a memory cell array. When a control circuit for controlling these bit and word lines reads/writes data from/to an assigned memory cell, float voltages of other memory cells may be disturbed, and thus error bits may occur (i.e., data (also referred to as “read data”) read from a memory cell by the control circuit is different from data (also referred to as “write data”) originally written into the memory cell). Or, when the flash memory is worn due to some factors (such as, unused for long-term, leakage of electricity or frequently erased), float voltages of memory cells may change and thus error bits may occur.
A memory storage apparatus is usually disposed with an error checking and correcting (ECC) circuit. When data is written, the ECC circuit generates an ECC code for the data. When subsequently the data is read, the ECC circuit performs error correcting and decoding (also referred to as an error correcting procedure) on the data according to the corresponding ECC code, so as to correct any error bit. However, the ECC circuit can only correct a limited number of error bits, and data cannot be corrected if the number of error bits in the data exceeds the number of error bits that can be corrected by the ECC circuit. In this case, the host system cannot correctly data read from the memory storage apparatus. The number of error bits will be increased due to the advancement in fabrication process and the characteristics of memory hardware structures (for example, the more data bits are stored in each memory cell of a MLC flash memory, the more error bits may occur). Thereby, how to ensure the accuracy of read data has become one of the major subjects in the industry.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.